The invention relates generally to nanoscale electronic devices, and more specifically to methods for testing and programming devices that contain molecular switches.
Over the past few decades, engineering advances have enabled the manufacture of semiconductor devices that have used progressively smaller transistors. Although this trend is likely to continue for the next few years, most researchers in the semiconductor industry believe that it will be impractical to manufacture transistors smaller than about 120 nanometers in length.
Researchers in the relatively new field of molecular electronics have been working to develop electronic devices using molecules that act as switches and memory devices. Because molecular switches are much smaller than even the smallest semiconductor transistor, researchers in this field believe that it will be possible to manufacture microprocessors and other computing devices that are much smaller and more powerful than would be possible using conventional semiconductor technology.
Although great advances have been made in the development of molecular switches and memory elements, these molecules have not yet been integrated into a practical device. One team of researchers, which includes J. M. Tour of Rice University and M. A. Reed of Yale University, has proposed integrating semi-randomly assembled molecular switches into xe2x80x9cnanocellsxe2x80x9d that act as arrays of logic gates. Thousands or millions of nanocells could be manufactured on a single chip.
As is shown in FIG. 1, a nanocell 100 is a small region (perhaps a square of 1 micron per side) on an insulating layer 101 and within this region many metallic and/or semiconducting nanoparticles 102 are bonded to the insulating layer and interconnected in a semi-random manner by molecular switches 104. Signals are transmitted to and from the nanocell via external connections 106.
It is impossible to predict a priori how the nanoparticles (and thus the external connections) will be interconnected by the molecular switches. Nanocell architecture is significantly different from more conventional architectures in that nanocell fabrication must be followed by device discovery and programming procedures. After fabrication, the logical relationship among the nanocell""s external connections must be determined. In addition, the nanocell must be programmed to enable it to perform a useful computational function. Theoretically, a Scanning Tunneling Microscope or an Atomic Force Microscope could be used to view and potentially influence the interconnections between the various nanoparticles and external connections. Such techniques would prove entirely impractical for large-scale devices with thousands or millions of nanocells.
Moreover, even where it may be possible to determine the logical relationship among external connections to a nanocell, it remains necessary to program the nanocell in order to ensure that its external connections have a useful logical relationship. It may also be necessary to xe2x80x9cre-programxe2x80x9d or modify the nanocell so that its external connections assume different logical relationships. For example, a nanocell that acts as a logical xe2x80x9cANDxe2x80x9d gate may need to be reprogrammed to operate as an adder or a xe2x80x9cNANDxe2x80x9d gate. Given the nanocell""s relatively small number of external connections and large number of molecular switches, conventional addressing and programming techniques fail to produce operable, programmed nanocells or nanocell based devices.
This invention provides methods for discovering a connectivity relationship among external connections to a two dimensional logic cell, such as a nanocell. In one embodiment, a voltage is applied to a selected, contiguous set of one or more of the external connections. The total current flow (TCF) received by the remainder of the external connections is measured; if the measured total current flow (TCF) falls below a threshold value (TV), that contiguous set of external connections is grouped together and thereafter treated as a single connection. These steps may be repeated for different contiguous sets of external connections until the desired level of characterization has been determined.
When a sufficient number of contiguous sets have been selected and tested according to the invention, the resultant connection groupings may then be used to derive the logical relationship among the external connections. In one embodiment, the connection groupings are used to generate a model of the logical relationships among the external connections represented as a Boolean expression using an Ordered Binary Decision Diagram (OBDD).
Alternate embodiments relate to methods for programming a series of interconnected devices, including the case in which the series of interconnected devices is a series of molecular switches contained within a nanocell. In one embodiment, a first voltage pulse is applied to an input to the interconnected devices, most or all of which are in an initial or first state. This first voltage pulse has a polarity, magnitude and time duration sufficient to cause a number of the devices to switch to a second state. A second voltage pulse of a shorter duration and opposite polarity may then be applied to the input thereby causing some of the previously switched devices to return to the first state. Subsequent voltage pulses of alternating polarity and progressively shorter duration may then be applied to the input until the programming is complete. Logic cells, including nanocells, programmed by the inventive methods are considered to be taught in this invention.